The present invention relates to the field of computer systems and more particularly to small computer systems.
Typical small computer systems have a central processing unit (CPU), main storage, a display, and various input/output (I/O)) devices (such as a keyboard, a printer and disk memory) connected together by buses. I/O devices typically connect to an I/O bus through device controllers such as a display controller, a disk controller and, when direct memory access (DMA) is employed, a DMA controller.
Computer systems, both small and large, are controlled by software in various forms. The operating system (OS) software functions as the interface between application program software and the computer hardware. In small systems, the software for controlling I/O devices is known as the basic input/output system (BIOS).
The BIOS typically includes self-test routines, device-handling routines, and system-service routines. The self-test routines are executed to ensure reliable operation of the system. The device handling routines control the operation of input/output devices. The system service routines provide program loading, memory size determination, equipment determination, time-of-day clock, screen function, and other system services.
Communication between the central processing unit and an I/O device typically involves execution by the central processing unit of an I/O instruction. Each I/O instruction is decoded to initiate read or write operations with an I/O device.
Computer systems, both small and large, have bus architectures that depend upon physical attributes such as board size, connector type, arbitration methods, synchronization protocols, transfer protocols, semiconductor technologies, and power and performance requirements. In small computer systems, many or all of the I/O devices connect to a common I/O bus where only one device at a time has access to the common I/O bus.
For an I/O bus, priority schemes are employed to determine which I/O device is to have access to the bus when more than one I/O device is in contention for the bus. Frequently, the central processing unit is given lowest priority so that when direct memory access (DMA) occurs between a disk and main storage, the central processing unit is forced to release control of the I/O bus.
Computer systems of all sizes have generally employed, in addition to an I/O bus, a number of special-purpose buses since a single general-purpose bus has been inadequate for satisfactory operation and performance.
Typically, in small computer systems, a dedicated memory bus is employed to optimize transfers between the central processing unit and main storage, a dedicated I/O bus is provided to optimize transfers to and from I/O devices and a display bus is provided to optimize transfers to a display. Other buses may also be provided. For example, extension buses are used to connect a number of physical modules together to form a single virtual module. Extension buses add bandwidth to the system and thereby reduce the load on other system buses.
Each bus in the computer system is characterized by a number of parameters. Bus clock speed is one bus parameter. Different semiconductor technologies are used as a function of bus clock speed to drive buses. The semiconductor technologies include CMOS (complementary metal oxide semiconductor), TTL (transistor-transistor logic), ECL (emitter-coupled logic), and BTL (backplane transceiver logic).
Other bus parameters are data width, address width, control line number and multiplexing. Typically, the data width of the bus is matched to the data width of the central processing unit. Processors of 16-bit generally match to 16-bit or more buses; 32-bit processors match to 32 bit or more buses, and so forth.
The number of bus pins is another bus parameter. The number of bus pins has been reduced by using buses that multiplex addresses and data for a particular bus. Multiplexed buses transfer data and addresses using the same bus lines for addresses and data.
Bus bandwidth is another bus parameter. Bandwidth of a bus is measured by measuring the bus performance when the system executes an application program. A useful measurement of bus performance is obtained by dividing the sustainable bus bandwidth by the number of pins used by the bus thereby giving the transfer rate per pin.
Another factor affecting bus architecture is the presence of cache memory. Cache memory both improves access time and eliminates duplicate memory accesses thereby reducing bus traffic.
One conventional small system is represented by Advanced Micro Devices' (AMD) AM286LX Integrated Processor which employs a conventional architecture having three separate buses. The IBM PC XT/AT architecture is another conventional multibus design based on maximizing system performance without regard to size or power requirements.
As the designs of personal computers evolve, smaller and smaller unit sizes are resulting. For pocket and handheld computers, a premium is placed on both small unit size and low power.
A conventional approach to reducing the size of a computer system is to integrate as much of the computer as possible into a chip set comprised of a small number of semiconductor chips or into a single semiconductor chip. Presently, the technology has progressed to the level of integration that permits a microprocessor to be integrated with other system components but has not progressed to the level of integration that permits an entire PC computer to be integrated into a single semiconductor chip.
Irrespective of the level of integration, in order for functions within chips to be useful, access to those functions must be provided through I/O pins. Therefore, as the level of integration increases, the number of pins on a semiconductor chip tends to increase also.
In order to significantly reduce the size of small systems, the number of I/O pins needs to be reduced in conjunction with an increased level of integration. Furthermore, these (decreased pins and increased integration) changes must be accomplished without degrading the functionality or without significantly impacting the performance of the system.
Conventional small system architectures utilize separate special-purpose buses for interfacing to devices with different parameters such as different speeds and different addressing characteristics. For a typical example, the ISA bus is designed to interface with standard PC XT/AT peripherals while the memory bus is designed to interface with DRAM memory. Also separate special-purpose buses for video memory and internal high-speed peripherals are conventional. The use of these different types of special-purpose buses in conventional highly-integrated systems requires use of many I/O pins and the presence of these I/O pins inhibits making smaller and more lightweight systems.
The "smaller than notebook" (palm-top) computers in addition to being smaller and more lightweight than conventional systems also require low power consumption so as to have long battery life. These requirements are difficult to achieve using the multiple numbers of special-purpose buses of conventional PC computers.
One function that requires excessive bus activity is refreshing of DRAM. Typically, DRAM must be refreshed at a rate of once ever 15.625 microseconds (512 refresh cycles in 8 milliseconds). For an XT, each refresh cycle is approximately 1 microsecond. Therefore, over 6% of the bus bandwidth of a PC/XT computer may be required to perform DRAM refresh if the refresh occurs over the bus.
Techniques have been used to reduce the refresh bandwidth requirements by shortening the refresh cycle of PC/XT, for example, from 1 microsecond to 500 nanoseconds. However, it is believed that no attempt has been made to eliminate the requirement for the bus altogether. Furthermore, with the introduction of the PCMCIA PC Card standard, and the definition within that standard of execute In Place (XIP) whereby software directly executes from PC Cards, DRAM refresh bandwidth requirements use much needed bus bandwidth that would be better used by slower PC Cards.
In typical computer systems, a keyboard scanning sub-system includes a dedicated microprocessor or microcontroller for scanning a keyboard switch matrix. These keyboard scanning sub-systems normally operate at relatively low frequencies, as compared to the main processor frequency, and are idle much of the time waiting for a depressed key input. Even though idle, conventional keyboard sub-systems consume substantial amounts of power which is wasted when the keyboard is idle.
In accordance with the above background, there is a need for an improved architecture for small systems that reduces both size and power consumption while providing good performance.